CMOS circuits are used in a variety of integrated circuit (IC) applications. A CMOS process can be used to fabricate many different sorts of functionality, such as memory, logic, and switching, and thus CMOS techniques are particularly desirable in applications where an IC includes several different types of functional blocks.
One family of ICs employing CMOS fabrication techniques are programmable logic devices (PLDs). PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these PLDs, the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
PLDs and other ICs that are specialized to be radiation tolerant are desirable for certain applications. Such ICs are often referred to as single event upset (SEU) tolerant ICs, heavy ion tolerant (HIT) ICs or radiation-hardened ICs. An SEU arises when a heavy ion or high-energy particle, such as an alpha particle or neutron, hits a memory cell, charging internal nodes of the memory cell that can change the memory state. For convenience of discussion, an SEU will be referred to as an “ion hit,” whether it involves an ion or other high-energy particle causing the error.
Two basic approaches to improve SEU tolerance have been tried. One approach is commonly called “resistive hardening;” however, resistive hardening can significantly degrade latch performance. Another disadvantage arises if a standard CMOS fabrication has to be modified to accommodate a resistively hardened IC. It is highly desirable that SEU tolerant ICs be made using standard CMOS fabrication processes.
Another approach to improve SEU tolerance is commonly called “design hardening.” Design hardening generally refers to laying out a memory cell or other circuit to improve recovery of data after ion hits. A general discussion of design hardening is found in the paper entitled Two CMOS Memory Cells Suitable for the Design of SEU-Tolerant VLSI Circuits, by Velazco et al., IEEE Transactions on Nuclear Science, Vol. 41, No. 6 (December 1994), the disclosure of which is hereby incorporated by reference in its entirety for all purposes.
In design hardening, redundant storage bits are located apart from each other, maintaining a source of initial data after an SEU upsets one of the storage bits. Many variations are known, using sixteen-, fourteen- and twelve-transistor SEU tolerant memory cells.
FIG. 1 is a circuit diagram of a prior art twelve-transistor SEU tolerant memory cell 150. As used herein, “twelve-transistor memory cell” refers to both the storage devices N1, N2, N3, N4, P1, P2, P3, P4 and the access devices T1, T2, T3, T4. Those of skill in the art of SEU resistant memory cells appreciate that the number of access devices is not always included in the transistor count or shown in the memory cell circuit diagram. The operation of the memory cell 150 will be familiar to those of skill in the art. A detailed description of a similar SEU resistant memory cell is described in U.S. Pat. No. 5,570,313 by Masson et al. and in U.S. Patent Application No. 2006/0056220 A1 by Roche et al., the disclosures of which are incorporated herein by reference in their entirety for all purposes. A detailed description of the electrical operation of the circuit is therefore omitted.
The memory cell circuit 150 has data terminals d, db (“data BAR”), output terminals Q, QQb, and internal nodes 152, 154 that store values Qb and QQ, respectively. A data value is a digital zero or digital one value, and the bar value is the opposite value. For example, if Q=1, then Qb=0. QQ saves a redundant value of Q, and QQb saves a redundant value of Qb. The values stored at the nodes are utilized in restoring the state of the memory cell if a node is upset by an SEU.
Since QQ has the same value of Q, and QQb has the same value of Qb, other nodes could be used for the outputs of the memory cell 150. For example, instead of Q and QQb being the nodes that are output, as shown in FIG. 1, the outputs could be nodes QQ and QQb, nodes Q and Qb, or nodes QQ and Qb. Furthermore, in a memory array having several similar memory cells defined in the silicon layer, some memory cells in the array may interface to other portions (circuits) of an IC through nodes Q and Qb, and other memory cells may interface to other portions or the IC through nodes QQ and Qb, for example.
Redundant data storage nodes are used for storing information. If data stored in one node is changed by an ion hit, the redundant node restores the other node to its initial value (state). This protects the data stored in the memory cell from ion hits as long as the data values stored in both of the redundant nodes are not simultaneously changed by an ion hit. It is desirable to physically separate redundant nodes to avoid both nodes from being affected by a single ion hit.
An ion hit creates charge in the silicon of the memory cell. This charge can upset the data value stored at a node by changing the voltage at that node. As the devices used in memory cells shrink, the amount of charge required to upset a stored data value also decreases. Charge is generated about a radius of the path of the ion. Although this charge radius depends on the energy of the ion, it is generally desirable to separate redundant nodes in SEU tolerant memory cells by at least one micron.
As the design technology decreases for IC production, a memory cell layout appropriate for a larger technology design dimension (e.g., 90 nm technology) might not provide adequate SEU tolerance when reduced to a smaller design dimension (e.g., 65 nm technology) product. For example, an SEU tolerant cell layout that provides sufficient spacing between redundant nodes in a 90 nm design might provide insufficient spacing when reduced to a 65 nm design.
Therefore, memory cells suitable for small geometry (small design technology) ICs that provide SEU tolerance is desirable.